Sowells-Boone, E., & Seay, C., & Brown, D. R. (2016, June), A Novel Technique for Low-Power Electronic System Design  Paper presented at 2016 ASEE Annual Conference & Exposition, New Orleans, Louisiana. 10.18260/p.26385

\bibitem{asee_peer_26385}
  Sowells-Boone, E., \& Seay, C., \& Brown, D. R. (2016, June), \emph{A Novel Technique for Low-Power Electronic System Design}
  Paper presented at 2016 ASEE Annual Conference \& Exposition, New Orleans, Louisiana.
  10.18260/p.26385

Evelyn Sowells-Boone, Cameron Seay, and Dewayne Randolph Brown.  "A Novel Technique for Low-Power Electronic System Design".  2016 ASEE Annual Conference & Exposition, New Orleans, Louisiana, 2016, June.  ASEE Conferences, 2016.  https://strategy.asee.org/26385 Internet.  14 May, 2024

\bibitem{asee_peer_26385}
  Evelyn Sowells-Boone, Cameron Seay, and Dewayne Randolph Brown.
  "A Novel Technique for Low-Power Electronic System Design".
  \emph{2016 ASEE Annual Conference \& Exposition, New Orleans, Louisiana, 2016, June}.
  ASEE Conferences, 2016.
  https://strategy.asee.org/26385 Internet.  14 May, 2024

@INPROCEEDINGS{asee_peer_26385
author = "Evelyn Sowells-Boone, Cameron Seay, and Dewayne Randolph Brown"
title = "A Novel Technique for Low-Power Electronic System Design"
booktitle = "2016 ASEE Annual Conference \& Exposition"
year = "2016"
month = "June"
address = "New Orleans, Louisiana"
publisher = "ASEE Conferences"
note = {https://strategy.asee.org/26385}
number = {10.18260/p.26385}
}

TY  - CPAPER
AB  - The central focus of digital system design engineers over the past two decades has been on the trade-offs between the power/energy and performance of the circuits implemented in current and emerging nanometer-scale VLSI technologies. A number of techniques have been developed to address this design challenge; one approach is based on a class of asynchronous pipelined digital circuit structures that are called self-timed. The dynamic power/energy dissipation is reduced in this realization, relative to synchronous implementations, because all clocks are generated locally and circuit timing and control is event driven. The performance of these circuits can exceed synchronous realization because it is based on the average intrinsic timing of the circuit instead of its worst case timing that is used to set the clock frequency in synchronous systems. The circuit design process used to determine the device sizing in self-timed circuits/systems is typically the same as that used for synchronous realizations. The input distribution is not considered in this process. A novel self-timed circuit design technique that out performs previously proposed approaches is presented in this paper. The input data distribution is used in the proposed technique to optimize the circuit performance for the respective input data set probability distribution.
AU  - Evelyn Sowells-Boone
AU  - Cameron Seay
AU  - Dewayne Randolph Brown
CY  - New Orleans, Louisiana
DA  - 2016/06/26
PB  - ASEE Conferences
TI  - A Novel Technique for Low-Power Electronic System Design
UR  - https://strategy.asee.org/26385
DO  - 10.18260/p.26385
ER  -