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Enhancing Student Understanding of Digital logic and Computer Architecture Through Turing Complete Game Challenges

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Conference

2024 ASEE North Central Section Conference

Location

Kalamazoo, Michigan

Publication Date

March 22, 2024

Start Date

March 22, 2024

End Date

March 23, 2024

Tagged Topic

Diversity

Page Count

11

DOI

10.18260/1-2--45615

Permanent URL

https://peer.asee.org/45615

Download Count

15

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Paper Authors

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Eric McKanna Ohio Northern University

biography

Firas Hassan Ohio Northern University

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Firas Hassan is an associate professor at Ohio Northern University. He got his Ph.D. from The university of Akron. His research interest are in the area of embedded computing of real-time image processing techniques.

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Abstract

Enhancing Student Understanding of Digital logic and Computer Architecture Through Turing Complete Game Challenges

Turing Complete is a game released on the steam platform designed to teach digital logic and computer architecture concepts through a series of challenges and problems. Its skill-tree style approach covers topics like digital logic, binary arithmetic, and memory. The end goal is to create a turing complete computer through building blocks developed during each different section of the tree. In this paper, we suggest adapting and modifying problems from the game to emphasize key comprehension points in the students’ coursework to both gauge understanding and build a more dynamic skill-set with logic gates. In addition to being a superb source of content for labs or homework assignments, the game also provides students with an excellent sandbox and simulation tool to develop and experiment with their own ideas.

For digital logic, the paper will detail an example of a challenge within the game prompting students to devise a decoder that produces a true output when a minimum of 2 out of 4 input bits are set to high. Initially it can be introduced during the study of Karnaugh maps (Kmaps), this challenge can later be evolved by the semester's end into a broader task: constructing a decoder that yields a true output for n high bits out of a total of 32 input bits. Successfully solving this advanced problem necessitates the utilization of higher-level components such as shift registers, accumulators, and comparators, which are comprehensively explained in later segments of the course curriculum.

Within the lab setting of computer architecture, students engage in the creation and simulation of various processor versions, including 32-bit single cycle, multicycle, and pipelined iterations of a RISC-V processor. Moreover, they delve into cache mechanisms encompassing direct, N-associative, and fully associative models, along with the exploration of translation lookaside buffer functionality. This paper showcases how students could utilize the Turing complete game to independently construct an 8-bit processor and execute a test program on it. Additionally, it illustrates the potential of the game's sandbox feature in facilitating simulations related to complex concepts like caches. These activities serve as examples of supplementary resources augmenting the laboratory segment of the course.

The paper will incorporate a survey conducted to evaluate the students' response to the potential integration of this game into future iterations of the curriculum, encompassing participants from both courses.

McKanna, E., & Hassan, F. (2024, March), Enhancing Student Understanding of Digital logic and Computer Architecture Through Turing Complete Game Challenges Paper presented at 2024 ASEE North Central Section Conference, Kalamazoo, Michigan. 10.18260/1-2--45615

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