Liu, C. C. (2015, June), Teaching Digital Designs by Building Small Autonomous Robotic Vehicles Using an FPGA Platform   Paper presented at 2015 ASEE Annual Conference & Exposition, Seattle, Washington. 10.18260/p.24809

\bibitem{asee_peer_24809}
  Liu, C. C. (2015, June), \emph{Teaching Digital Designs by Building Small Autonomous Robotic Vehicles Using an FPGA Platform }
  Paper presented at 2015 ASEE Annual Conference \& Exposition, Seattle, Washington.
  10.18260/p.24809

Cheng Chih Liu.  "Teaching Digital Designs by Building Small Autonomous Robotic Vehicles Using an FPGA Platform ".  2015 ASEE Annual Conference & Exposition, Seattle, Washington, 2015, June.  ASEE Conferences, 2015.  https://peer.asee.org/24809 Internet.  28 May, 2024

\bibitem{asee_peer_24809}
  Cheng Chih Liu.
  "Teaching Digital Designs by Building Small Autonomous Robotic Vehicles Using an FPGA Platform ".
  \emph{2015 ASEE Annual Conference \& Exposition, Seattle, Washington, 2015, June}.
  ASEE Conferences, 2015.
  https://peer.asee.org/24809 Internet.  28 May, 2024

@INPROCEEDINGS{asee_peer_24809
author = "Cheng Chih Liu"
title = "Teaching Digital Designs by Building Small Autonomous Robotic Vehicles Using an FPGA Platform "
booktitle = "2015 ASEE Annual Conference \& Exposition"
year = "2015"
month = "June"
address = "Seattle, Washington"
publisher = "ASEE Conferences"
note = {https://peer.asee.org/24809}
number = {10.18260/p.24809}
}

TY  - CPAPER
AB  -  An Instructional Digital Systems Design Course Incorporating Xilinx Design                       Suite and Digilent FPGA BoardsAbstractMany digital systems design courses and texts use a hardware description language(HDL) model of a processor to demonstrate digital design principles. Mostprocessors design focus on the implementation of a computer architecture andinstruction set. These topics are presented in such a way that discourages studentsto use processor systems to create real-world applications. What is needed is apredefined processor IP core with off-the-shelve peripheral devices that can beused immediately to implement student’s ideas with standard FPGA hardware.Instructional digital systems have been developed with the Xilinx ISE andembedded system development (EDK) design suite. The programming languagesto develop project examples are Verilog HDL and C languages. The courseobjectives are separated into two teachable subsets: the digital systems that do notneed a microprocessor to run while others require a microprocessor to run on areal-time application. Laboratory experiments such as reconfigurable processors,peripheral IP cores and interfacing techniques for the following sensors arediscussed; 3-axis accelerometer, gyro, magnetometer, contactless infrared remoteobject, Bluetooth wireless communication between Xilinx processor and anapplication run on Android phone and tablet.The reconfigurable microprocessor system-on-chip or a FPGA-based processorsystem is a new and increasing important trend. It facilitates rapid prototyping ofdigital systems design. FPGAs are equipped with reconfigurable on-chip memoryblocks, peripherals and interconnection circuitry. FPGAs also allow the integrationof a large number of functions such as audio and video encoding, roboticcontrollers design, image processing, and internet access.The instructional digital systems design is now in its third iteration with an updatedembedded design with the following peripherals: 32-bit MicroBlaze processor, 32-bit ARM processor IP, analog and digital electronic components. Analogperipherals include operator control switches, buttons, LED lights, 4 by 4 16-keykeypads and motors. Digital components include analog-to-digital converters,USB-UART ports for communication between soft-core processors and externalhardware components. Results from student homework assignments and projectsindicate that students are able to successfully prototype a system-on-chip usingFPGAs.
AU  - Cheng Chih Liu
CY  - Seattle, Washington
DA  - 2015/06/14
PB  - ASEE Conferences
TI  - Teaching Digital Designs by Building Small Autonomous Robotic Vehicles Using an FPGA Platform 
UR  - https://peer.asee.org/24809
DO  - 10.18260/p.24809
ER  -