VLSI Design, Verification and Fabrication of an Arithmetic Logic Unit (ALU) Using the Cadence Virtuoso: A Case Study

Nian Zhang; Wagdy H Mahmoud; Tewodros Mekbib Mamo

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Conference: 2022 Spring ASEE Middle Atlantic Section Conference
Location: Newark, New Jersey
Publication Date: April 22, 2022
Start Date: April 22, 2022
End Date: April 23, 2022
Page Count: 15
DOI: 10.18260/1-2--40081
Permanent URL: https://strategy.asee.org/40081
Download Count: 818

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Nian Zhang

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Dr. Nian Zhang is a Professor in the Department of Electrical and Computer Engineering at the University of the District of Columbia (UDC), Washington, D.C., USA. She received her Ph.D. degree in Computer Engineering from Missouri University of Science & Technology, USA. Her research interests include computational intelligence, machine learning, deep learning, supervised and unsupervised learning, classification, clustering, and optimization, neurodynamic optimization, and various application fields including big data science, time series prediction, biomedical engineering, and autonomous robot navigation. Dr. Zhang was awarded numerous federal grants from the National Science Foundation, Department of Defense, and National Institutes of Health as the PI/Co-PI, accumulating over $4.5 million in research grant funds. Dr. Zhang serves as an Associate Editor for the IEEE Transactions on Cybernetics (IF: 11.448), IEEE Transactions on Neural Networks and Learning Systems (IF: 10.451), and Knowledge-based Systems (IF: 8.038). She also serves on the Editorial Board for the Complex & Intelligent Systems (IF: 4.927). In addition, Dr. Zhang serves as the Chair of the IEEE Computational Intelligence Society (CIS) Task Force on "Interdisciplinary Emergent Technologies" and the Vice Chair of the IEEE CIS Adaptive Dynamic Programming and Reinforcement Learning Technical Committee. She regularly serves as the Program Chair, Publications Chair, and Special Sessions Chair of the IEEE technically co-sponsored conferences such as ICACI, ICICIP, ICIST, and ISNN. Dr. Zhang received the UDC’s faculty recognition awards for Excellence in Research Award, Excellence in Teaching Award, and Outstanding Undergraduate Research Mentorship Award in three consecutive years.

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Wagdy H Mahmoud P.E. University of the District of Columbia

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Wagdy H. Mahmoud is a Professor of electrical engineering at the Electrical Engineering Department at UDC. Mahmoud is actively involved in research in the areas of reconfigurable logic, hardware/software co-design of a system on a chip using reconfigurable logic, application-specific integrated circuits (ASIC), digital logic design, image compressions, digital signal processing, computer architecture, embedded systems, system on a chip, and renewable energy.

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Tewodros Mekbib Mamo University of the District of Columbia orcid.org/0000-0003-1478-2544

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Research Interests: Mr. Mamo's research interests are computer hardware design (ISA), computer software design, Digital systems and communications systems design, guidance navigation and control, path planning, Fuzzy logic, application of machine learning on modern control systems and FPGA based systems design.

Career in Brief: Mr. Tewodros Mamo is a first-year Doctoral student at University of The District of Colombia majoring in Electrical Engineering and Computer Science. He received his B.S. in general engineering focused on Aerospace engineering from the University of Maryland Eastern Shore in 2018. Mr. Mamo then served as a K12 engineering teacher in Baltimore, Maryland and in Washington DC from 2018 to 2019. In 2019, he joined the University of the District of Colombia as an Electrical Engineering M.S. student and completed his studies with an emphasis on VLSI design in 2021.

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Abstract

VLSI Design, Verification and Fabrication of an Arithmetic Logic Unit (ALU) Using the Cadence Virtuoso: A Case Study Abstract Although the Cadence Virtuoso has been widely used in many universities, there is lack of a shareable publication, document, or tutoring video on the very large-scale integration (VLSI) design, verification and fabrication. Few online tutorials or tutoring video are quite outdated. They either cannot be used for step-by-step guideline, or they only cover part of the entire design flow, which doesn’t meet designer’s need. The lack of up to date publication or document has caused a huge barrier for universities to teach a VLSI lab. Due to a severe discrepancy in procedure and parameter setting, instructors have to report technical cases to the Cadence technical support center, and then spend significant time troubleshooting problems with the remote assistance from the Cadence engineers. This has greatly affected the progress of lab teaching and student learning. In addition, there is very few sources of educational tutorials of adding pad frame, which is a complex but extremely important component before fabrication. Therefore, there is an urgent need to create and disseminate a shareable publication or document on VLSI design, verification and fabrication with the latest version of Cadence Virtuoso. This paper promotes the needs of a comprehensive study on the newest version of Cadence Virtuoso, a state-of-the-art CAD tool for VLSI design. An 8-bit arithmetic logic unit (ALU) is used as a proof-of-concept example to go through the major VLSI design flow, including schematic capture, pre-layout simulation, physical layout, extract, design rule check (DRC), and layout vs. schematic (LVS). In addition, since this specific ALU is designed to perform three logical operations (i.e. AND, OR, and XOR) and two arithmetic operations (i.e. addition and subtraction), their respective schematic, symbol, testbench, pre-layout simulation, physical layout, post-layout simulation results are demonstrated with detailed snapshots. Moreover, the design layout is wired to a 40-pin MOSIS Tiny Chip pad frame. The ALU circuit is then simulated along with the pad frame and the simulation results are analyzed. Universities and designers around the world will find it an invaluable document, which ensures an efficient and fast VLSI design, verification and fabrication using the latest Cadence Virtuoso software.

Citation
Format

Zhang, N., & Mahmoud, W. H., & Mamo, T. M. (2022, April), VLSI Design, Verification and Fabrication of an Arithmetic Logic Unit (ALU) Using the Cadence Virtuoso: A Case Study Paper presented at 2022 Spring ASEE Middle Atlantic Section Conference, Newark, New Jersey. 10.18260/1-2--40081

TY - CPAPER
AB - VLSI Design, Verification and Fabrication of an Arithmetic Logic Unit (ALU) Using the Cadence Virtuoso: A Case Study

Abstract
Although the Cadence Virtuoso has been widely used in many universities, there is lack of a shareable publication, document, or tutoring video on the very large-scale integration (VLSI) design, verification and fabrication. Few online tutorials or tutoring video are quite outdated. They either cannot be used for step-by-step guideline, or they only cover part of the entire design flow, which doesn’t meet designer’s need.
The lack of up to date publication or document has caused a huge barrier for universities to teach a VLSI lab. Due to a severe discrepancy in procedure and parameter setting, instructors have to report technical cases to the Cadence technical support center, and then spend significant time troubleshooting problems with the remote assistance from the Cadence engineers. This has greatly affected the progress of lab teaching and student learning. In addition, there is very few sources of educational tutorials of adding pad frame, which is a complex but extremely important component before fabrication. Therefore, there is an urgent need to create and disseminate a shareable publication or document on VLSI design, verification and fabrication with the latest version of Cadence Virtuoso.
This paper promotes the needs of a comprehensive study on the newest version of Cadence Virtuoso, a state-of-the-art CAD tool for VLSI design. An 8-bit arithmetic logic unit (ALU) is used as a proof-of-concept example to go through the major VLSI design flow, including schematic capture, pre-layout simulation, physical layout, extract, design rule check (DRC), and layout vs. schematic (LVS). In addition, since this specific ALU is designed to perform three logical operations (i.e. AND, OR, and XOR) and two arithmetic operations (i.e. addition and subtraction), their respective schematic, symbol, testbench, pre-layout simulation, physical layout, post-layout simulation results are demonstrated with detailed snapshots. Moreover, the design layout is wired to a 40-pin MOSIS Tiny Chip pad frame. The ALU circuit is then simulated along with the pad frame and the simulation results are analyzed. Universities and designers around the world will find it an invaluable document, which ensures an efficient and fast VLSI design, verification and fabrication using the latest Cadence Virtuoso software.
AU - Nian Zhang
AU - Wagdy H Mahmoud P.E.
AU - Tewodros Mekbib Mamo
CY - Newark, New Jersey
DA - 2022/04/22
PB - ASEE Conferences
TI - VLSI Design, Verification and Fabrication of an Arithmetic Logic Unit (ALU) Using the Cadence Virtuoso: A Case Study
UR - https://strategy.asee.org/40081
DO - 10.18260/1-2--40081
ER -