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The Utility of a Structured Hardware Language as a Pedagogical Tool

Mehran Massoumi

Department of Mathematics & Computer Science California State University, Hayward Hayward, CA 94542 massoumi@sbcglobal.net

Abstract: Senior/Graduate courses in Computer Organization and Design are most effective if they employ a Hardware Description Language (HDL) capable of modeling Register Transfer (RT) behavior. Such a language should allow description of design details and evaluation of architectural alternatives without sidetracking the students with esoteric constructs. Due to the momentum gained by Verilog and VHDL, both IEEE standards, one tends to rule out any non- standard and to-the-point languages, even though their benefits are readily observed. Moreover, what is really needed is a structured language that does not overwhelm the students with complex semantics and yet is powerful enough to allow functional capture and concise manipulation of the design. In this paper, a structured HDL is introduced. Experiences in using this language in a graduate course as well as the student’s reactions will be discussed.

Introduction:

Throughout the decades of digital computer history, various symbols and notations have been developed for capturing the logical behavior of digital circuits while avoiding their electronic and fabrication details. The primary motivation has been to facilitate documentation, design, and analysis of complex systems. A few examples of such notations are schematics, Boolean expressions, timing charts, state transition tables, block diagrams, and hardware description languages. Although most of these notations are being used in practice today, hardware description languages have received remarkable acceptance from the design community since early1990s.

A hardware language can serve as a principal means of communication between members of a design team. The conciseness and readability of HDLs minimize the need for any natural language, and more error prone, discussion of the design. Furthermore, HDLs are commonly used for design entry into a variety of analysis and synthesis software tools, which greatly facilitate the verification and realization of any given design. It should be noted that a HDL is a language and only a language and has no apparent algebraic structure in terms of guiding the user to a minimal implementation. However, with practice, one will readily arrive at modeling techniques that yield more efficient hardware realizations.

Designers today routinely use VHDL[4,6] and Verilog[2,3,5], both IEEE standard HDLs, in their design flows. However, the role of these languages in teaching Computer Organization and Design is not well defined or convincingly effective. Both Verilog and VHDL are complex and

“Proceedings of the 2005 American Society for Engineering Education Annual Conference & Exposition Copyright2005, American Society for Engineering Education”

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Massoumi, M. (2005, June), The Utility Of A Structured Hardware Language As A Pedagogical Tool Paper presented at 2005 Annual Conference, Portland, Oregon. 10.18260/1-2--15292